Transmitter (Tx) SerDes Design Engineer — 224G/448G

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

Ciena’s WaveLogic family of products enables high-speed optical transmission solutions that are foundational to modern telecommunications networks. This role contributes to the continued advancement of high-speed circuit design for broadband fiber-optic systems within a vibrant team with a proven track-record of success over 30 years of evolution in high-speed circuits for broadband fiber-optic modems — the team that pioneered the world's first high-speed DAC and ADC analog macros for coherent fiber-optic products.  

We are looking for a hands-on Transmitter (Tx) SerDes Design Engineer to design and deliver our high-speed electrical transmitter macros for Mutlirate SerDes in the latest deep-submicron CMOS technologies.  

How you will make an impact: 

• Own schematic-level design and post-layout verification of the transmitter sub-blocks such as: high speed mux, output stage, serialization, clocking interface, and output driver 
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  Evaluate circuit topologies and recommend implementations based on tradeoffs across power, area, bandwidth, and technology constraints. 
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  Collaborate with layout and design engineers to deliver designs through full GDSII integration. 
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  Drive extraction-based post-layout simulations and validate transmitter performance (bandwidth, linearity/RLM, return loss, jitter, and power) across process, voltage, and temperature conditions. 
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  Own root-cause analysis of design- and post-layout performance gaps and implement the corrective design actions to meet specifications.   
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  Maintain block- and transmitter-level performance and power tracking against the agreed targets.  
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  rt test-chip, product bring-up and characterization. Partner with lab validation teams to correlate silicon results with simulations and suppo

The must haves: 

• Education: Bachelor’s degree in Electrical Engineering or Computer Engineering, or applicable scientific discipline. 
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  Experience: 5+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post-layout verification. 
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  Application of transmitter circuit building blocks including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits. 
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  Execution of post-layout and extraction-based simulations to validate performance across process, voltage, and temperature conditions. 
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  Delivery of analog circuit designs through silicon validation. 
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  Utilization of Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR-RC, and MMSIM. 
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  and within a team environment. Demonstrated written and verbal communication skills and ability to work independently

Nice to haves: 

• Experience: Application of 224G or 448G PAM4 or PAM6 SerDes and related OIF-CEI or IEEE standards. 
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  ontributing to transmitter architecture using MATLAB, Verilog-A, or C++. Experience c
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  of signal integrity, power integrity, channel, and package co-design methodologies, including use of EM tools such as HFSS or EMX. Application
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  Experience mentoring engineers within analog macro design teams. 
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  robing equipment. Experience with mixed-signal validation using high-speed measurement and p

Pay Range: The annual pay range for this position is $90,600 - $144,800

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.  Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.